STAFF Engineer- DEG Layout

2 days ago

Bengaluru, India Micron Full time

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Contributing to the development of new product opportunities by working on layout, and optimization of Memory/Logic/Analog circuits Layout design independently or lead functional block /Partition/Fullchip Overseeing and managing the layout process including floor-planning, placement, and routing Demonstrate commitment and responsibility towards the work/assignment, own the task and take proactive measures to finish the work as per the schedule Efficiently plan the task based on project timelines in agreement with project lead. Course correct the plan if there is any change in the task example ECOs Must be able tointerpret and cleanDRC, LVS and other PDV runs or toolswhenever requirement arises. Should be able to debug and resolvecomplex verification issues. Should be able to Identify gap or improvement area in current methodology and drive improvement. Ensure all the layout done and released from India team is as per quality guidelines, show continuous improvement in the quality of layout. should be able to train, mentor new joiners and other team members. Expert in technical and schedule perspective to review, plan, estimate and delegate the blocks. Responsible forrelease ofblock on time as per the quality guidelines. Create a culture to drive or inculcate new ideas/solutions and drive them independently till they are absorbed in the system or current flow. Working experience in multiple silicon-proven tape-outs with multimillion gate count designs. Hands-on experience in synthesis using Design Compiler or Genus. Experience in writing and modifying place and route tech files and calibrating with Calibre DRC. Proven experience in physical design, including floor planning, placement, clock tree synthesis, routing, and timing closure (both Synopsys and Cadence EDA tools). Experience in power planning, IR drop, and EM analysis. Experience in logic block and chip-level verification. Very good understanding of timing constraints and their closure in both low power and high-performance designs. Knowledge of standard cell libraries and liberty files. Ability to understand standard cell layouts and guide the team based on routing challenges to meet target PPA specifications. Strong skills in Perl, Tcl, and Python. Experience in design enablement, implementation flows, and methodologies for deep submicron technologies. Collaborating with cross-functional teams to deliver high-quality design solutions. Enhancing efficiency and performance of design projects. Excellent communication skills to convey complex ideas. Autonomous and capable of making timely decisions. Able to handle interruptions and maintain focus on goals. Collaborative team player who enjoys working with cross-functional teams. Innovative thinker who stays updated with industry trends and best practices. Leading and training a team of 3-5 members.

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