Asic Digital Design Engr, Ii

2 days ago

Hyderabad, India Synopsys Full time

40609BR
- INDIA - Hyderabad

**Job Description and Requirements**
- Knowledge of Verilog/System Verilog or any of the VMM/UVM/OVM methodologies is a plus- Knowledge of fundamental CMOS integrated circuit design is a plus
- Knowledge on fundamentals of circuit analysis, Mixed signal verification, EM/IR analysis and simulations. is a plus
- Understanding of semiconductor technology is plus.
- Familiar with VCS/Verdi simulation tools, Formal verification tool (vc_formal)
- Scripts skills such as Perl, Python preferred
- Domain knowledge of protocols sata/pcie/usb/ethernet/MPHY is a significant advantage
- Self-motivated, hardworking and innovative in bringing solutions to complex problems.

**Job Category**
- Engineering

**Country**
- India

**Job Subcategory**
- ASIC Digital Design

**Hire Type**
- Employee

  • Asic Physical Design Engr, Ii

    4 hours ago

    Hyderabad, India Synopsys Full time

    45701BR - INDIA - Hyderabad **Job Description and Requirements** **ASIC Physical Design Engr, II** **Job Description and Requirements** **Responsibilities**: - Oversees definition, design, verification, and documentation for ASIC development. Establishes architecture design, logic design, and system simulation. Defines module interfaces/formats for...

  • Senior ASIC RTL Designer

    4 days ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ years- Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.- Create micro-architecture specs and ensure designs meet performance, power, and area targets.- Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    5 days ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ years- Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.- Create micro-architecture specs and ensure designs meet performance, power, and area targets.- Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    5 days ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    7 days ago

    hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    7 days ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    7 days ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    6 days ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    3 days ago

    hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior asic rtl designer

    2 days ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ years- Design and develop synthesizable RTL using Verilog/System Verilog for complex ASIC/So C blocks.- Create micro-architecture specs and ensure designs meet performance, power, and area targets.- Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and...