Senior ASIC RTL Designer

15 hours ago

Hyderabad, India Eximietas Design Full time

Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT readiness.Collaborate with verification teams for test planning, debugging, and coverage closure.Integrate IPs into top-level SoC and resolve timing and functionality issues.Support emulation, FPGA prototyping, and silicon bring-up activities with cross-functional teams.

  • Senior ASIC RTL Designer

    10 hours ago

    hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    11 hours ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    7 hours ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    10 hours ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years - Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. - Create micro-architecture specs and ensure designs meet performance, power, and area targets. - Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA,...

  • Senior ASIC RTL Designer

    7 hours ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    1 day ago

    Hyderabad, Telangana, India Eximietas Design Full time ₹ 20,00,000 - ₹ 25,00,000 per year

    Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • ASIC RTL Design Engineer

    2 weeks ago

    Hyderabad, India ACL Digital Full time

    RTL (ASIC) Design EngineerExperience : 1-3 YearsLocation : HyderabadInterested,please share your updated resume to

  • ASIC RTL Design Engineer

    1 week ago

    Hyderabad, India ACL Digital Full time

    RTL (ASIC) Design Engineer Experience : 1-3 YearsLocation : HyderabadInterested,please share your updated resume to

  • ASIC RTL Design Engineer

    3 weeks ago

    Hyderabad, India ACL Digital Full time

    RTL (ASIC) Design Engineer Experience : 1-3 YearsLocation : HyderabadInterested,please share your updated resume to

  • ASIC RTL Design Engineer

    2 weeks ago

    hyderabad, India ACL Digital Full time

    RTL (ASIC) Design EngineerExperience : 1-3 YearsLocation : HyderabadInterested,please share your updated resume to janagaradha.n@acldigital.com