Senior ASIC RTL Designer

1 week ago

hyderabad, India Eximietas Design Full time

Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT readiness.Collaborate with verification teams for test planning, debugging, and coverage closure.Integrate IPs into top-level SoC and resolve timing and functionality issues.Support emulation, FPGA prototyping, and silicon bring-up activities with cross-functional teams.

  • Senior ASIC RTL Designer

    4 weeks ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ years- Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.- Create micro-architecture specs and ensure designs meet performance, power, and area targets.- Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    4 weeks ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior asic rtl designer

    3 weeks ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ years- Design and develop synthesizable RTL using Verilog/System Verilog for complex ASIC/So C blocks.- Create micro-architecture specs and ensure designs meet performance, power, and area targets.- Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and...

  • Senior ASIC RTL Designer

    4 weeks ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    4 days ago

    hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    4 days ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    1 week ago

    Hyderabad, Telangana, India Eximietas Design Full time ₹ 20,00,000 - ₹ 25,00,000 per year

    Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    2 weeks ago

    Hyderabad, Telangana, India, Telangana Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • ASIC RTL Design Engineer

    2 weeks ago

    Hyderabad, India Proxelera Full time

    Looking for your next big challenge in ASIC Design?We're hiring ASIC Design Engineers with 8–15 years of experience to join our team in Hyderabad!If you have expertise in RTL design, Verilog coding, SoC integration, synthesis, timing closure, and have completed at least one tape-out cycle, we'd love to connect with you.Location: HyderabadExperience: 8–15...

  • ASIC RTL Design Engineer

    6 days ago

    Hyderabad, India Proxelera Full time

    Looking for your next big challenge in ASIC Design?We’re hiring ASIC Design Engineers with 8–15 years of experience to join our team in Hyderabad!If you have expertise in RTL design, Verilog coding, SoC integration, synthesis, timing closure, and have completed at least one tape-out cycle, we’d love to connect with you.Location: HyderabadExperience:...