Asic Physical Design Engr, Ii
4 hours ago
45701BR
- INDIA - Hyderabad
**Job Description and Requirements**
**ASIC Physical Design Engr, II**
**Job Description and Requirements**
**Responsibilities**:
- Oversees definition, design, verification, and documentation for ASIC development. Establishes architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Examines equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to help development.**Requirements**:
**Job Category**
- Engineering
**Country**
- India
**Job Subcategory**
- ASIC Physical Design
**Hire Type**
- Employee
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Lead Physical Design Engineer
3 days ago
hyderabad, India MosChip® Full timeHe/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have...
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Lead Physical Design Engineer
3 days ago
Hyderabad, India MosChip® Full timeHe/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have...
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Lead Physical Design Engineer
3 days ago
Hyderabad, India MosChip® Full timeHe/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have...
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Lead physical design engineer
2 days ago
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Lead Physical Design Engineer
1 day ago
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Lead Physical Design Engineer
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