STA & Synthesis Engineer

1 week ago


Bangalore, India ACL Digital Full time

Looking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks Prime time constraint generation/development at Top level, full chip level and clean up. Multimode multi corner timing knowledge and timing closure at sub HM/block/top level. Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Scripting experience in Perl/TCL. Regards, Sneha



  • Bangalore Division, India ACL Digital Full time

    Looking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...


  • bangalore district, India ACL Digital Full time

    Looking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...


  • bangalore, India ACL Digital Full time

    Looking for STA & Synthesis Engineer.Exp.-3.5+yrs.Job Location- Bangalore.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Responsible to complete synthesis till final-opt with DFT insertionExperience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks...


  • Bangalore, India ACL Digital Full time

    Looking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. - Netlist and constraint sign in checks and validation. - Responsible to complete synthesis till final-opt with DFT insertion - Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low...


  • bangalore, India L&T Technology Services Full time

    L&T Technology is looking to hire for STA Engineers. Job Location : Bangalore Detailed JD is below ::JD For STA Engineer-6+ ’ experience • Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. • Can work closely with FE team for constraints development and constraints cleanup. • Work with...


  • bangalore, India L&T Technology Services Full time

    L&T Technology is looking to hire for STA Engineers. Job Location : Bangalore Detailed JD is below :: JD For STA Engineer-6+ ’ experience • Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. • Can work closely with FE team for constraints development and constraints cleanup. • Work with...

  • Lead STA

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    bangalore, India Cadence System Design and Analysis Full time

    BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization...

  • Lead STA

    5 days ago


    Bangalore, India Cadence System Design and Analysis Full time

    BE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...

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  • Lead STA

    3 days ago


    bangalore district, India Cadence System Design and Analysis Full time

    BE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...