Graduate digital engineer

FPGA Design Engineer We are seeking an RTL FPGA Engineer with a strong background in FPGA design, RTL development, and digital system design. The ideal candidate will have expertise in developing FPGA solutions using VHDL or SystemVerilog , along with solid experience in hardware verification and debugging. This role will involve designing RTL for complex...

The Digital Engineer is responsible for driving the digitalization of manufacturing and engineering processes across food and beverage operations. This role focuses on integrating smart technologies, automation systems, and data analytics to enhance productivity, traceability, and sustainability in line with Industry 4.0 principles. Design and implement...

Experience: 3 - 6 Years Notice period: Immediate Mandatory Experience in Full Chip Timing . Strong background in digital IC design , including floorplanning, placement, routing, clock tree synthesis, and optimization. Proficient in Innovus , ICC2 , and Fusion Compiler for place and route, timing closure, and physical design sign-off. Physical Design :...

Senior/Principal Memory Design Engineer Experience: 10+ Years About ACL Digital ACL Digital, part of the ALTEN Group , is a next-generation product engineering and semiconductor services company with global presence across 30+ countries. We specialize in ASIC/SoC design, memory IP, verification, embedded systems, automotive, 5G, AI/ML, and cloud solutions ,...

Full Chip Physical Design Engineer We are seeking a highly motivated and skilled engineer to join our SoC implementation team. You will be responsible for the physical design of complex ASICs and SoCs, working on full-chip floorplanning, integration, and signoff activities to meet aggressive PPA (Power, Performance, Area) goals. Drive full chip-level...

SOC RTL Design Verification Experience : 4 to 10 Years Development and verification of post-si validation sequences using C/C++ • Experienced with Verilog, System Verilog, and C or C++ • Candidate past experience requirements, • Should have experience in system-level Verification. • DDR prior experience is not mandatory. ACL Digital, a leader in...

ACL Digital is looking for "Senior Design Verification Engineers" Immediate to 30 days Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC. Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language...

Summary Graduate Engineer trainee is responsible for providing manufacturing and or engineering process support in accordance with documented procedures and practices Responsible for the development implementation improvement and continuous reinforcement that are utilized in the local business GE HealthCare is a leading global medical technology and digital...

Engineering Trainee – Civil (Immediate Joinee) Location: KK Nagar, Chennai Company: Seraphic Global Private Limited Contact: +91 95001 11113 Email: ramani@seraphicglobalgroup.com Employment Type: Full-Time (Immediate Requirement) About Us Seraphic Global Private Limited is a fast-growing multidisciplinary consultancy offering services in infrastructure...

Should be able to handle Full chip hashtag Added advantage for #Innovus with Minimum 4 years #PnR (timing/congestion/CTS issues), understanding of hashtag #IO ring, #package support, multi hashtag #voltage design. &## ;Deep understanding of the concepts related to hashtag #synthesis , place & route, hashtag #CTS , timing convergence, IR/EM checks and signoff...