Product Engineer

5 days ago

Bangalore, India ACL Digital Full time

Full Chip Physical Design Engineer We are seeking a highly motivated and skilled engineer to join our SoC implementation team. You will be responsible for the physical design of complex ASICs and SoCs, working on full-chip floorplanning, integration, and signoff activities to meet aggressive PPA (Power, Performance, Area) goals. Drive full chip-level physical design flow from RTL to GDSII. Manage static timing analysis (STA) at top level and work closely with timing owners for signoff. Handle power planning and power domain implementation (UPF/CPF-based). Bachelor's or Master’s degree in Electrical/Electronics/Computer Engineering or related field. ~3–6 years of experience in physical design with at least one full chip tapeout. ~ Strong knowledge of physical design concepts: floorplanning, CTS, routing, timing closure, IR drop, EM, DRC/LVS. ~ Proficiency in scripting languages like Tcl, Perl, Python, or Shell. ~ Familiarity with hierarchical design and ECO flows. Experience: 3 to 6 Years.

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