Senior Digital Design Verification Engineer

Senior Design Verification Engineer Location: Bangalore. Experience: 4 to 10 Years. Notice Period: Any. Perform verification of complex digital designs at block and system level. Develop testbenches using System Verilog/UVM for simulation and debugging. Create and execute comprehensive test plans for functional verification. Achieve coverage targets...

Senior Design verification Engineer Mandatory Skill : PCIE Experience : 5 years Design Verification Engineer responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Coverage: Achieve functional and code coverage targets through constrained random and directed...

Senior Design Verification Engineer Experience: 4 to 10 Years. Perform verification of complex digital designs at block and system level. Work closely with RTL design and architecture teams to identify issues. Experience with scripting languages like Python, Perl, or Tcl. Bachelor’s or Master’s degree in Electronics, Electrical, or related field....

Senior Design verification Engineer Mandatory Skill : PCIE Location : Bangalore Experience : 5 years Design Verification Engineer responsible for ensuring functional correctness of ASIC/So C designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/System Verilog to create testbenches, write test...

Hi All, ACL Digital is looking for " Senior Design Verification Engineers" Exp Level: 4+ years Notice period: Immediate to 30 days Location: Bangalore and Hyderabad Job Description: Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in...

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to

SOC RTL Design Verification Experience : 4 to 10 Years Development and verification of post-si validation sequences using C/C++ • Experienced with Verilog, System Verilog, and C or C++ • Candidate past experience requirements, • Should have experience in system-level Verification. • DDR prior experience is not mandatory. ACL Digital, a leader...

Hi All, ACL Digital is hiring #Senior #Design #Verification Engineer! Experience: 4 Years Location: Bangalore / Hyderabad Notice Period: Immediate to 30 Days Preferred! We're seeking experienced professionals ASIC/So C verification. If you have expertise in UVM/System Verilog, proficiency in scripting languages like Python/Perl/TCL, and a strong grasp...

Hi All, ACL Digital is looking for "Senior Design Verification Engineers" Exp Level: 4+ years Notice period: Immediate to 30 days Location: Bangalore and Hyderabad Job Description: Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in...

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to