RTL Design Engineer

4 days ago

Hyderabad, India ACL Digital Full time

Position: RTL Design Engineer Experience: 5 - 8 Years Qualifications: BE/Btech in ECE/EEE Responsibilities - The candidate should have strong RTL design experience. Strong design experience in Ethernet IPs or Ethernet protocol domain. Knowledge in Verilog/VHDL languages Scripting languages: TCL/Perl/Python (any one). Knowledge of AXI Protocols.

  • Senior ASIC RTL Designer

    1 week ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    1 week ago

    hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    1 week ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    1 week ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    1 week ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years - Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. - Create micro-architecture specs and ensure designs meet performance, power, and area targets. - Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA,...

  • Senior ASIC RTL Designer

    1 week ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    1 week ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    6 days ago

    hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    1 week ago

    Hyderabad, India Eximietas Design Full time

    Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

  • Senior ASIC RTL Designer

    1 week ago

    Hyderabad, Telangana, India Eximietas Design Full time ₹ 20,00,000 - ₹ 25,00,000 per year

    Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...