Sta engineer

1 month ago

Bengaluru, India UST Full time
Who we are:
At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at www. UST.com
W e are looking to fill a Strong Synthesis & Timing Closure Engineer who has worked on:
Experience: 6+ years of experience in Synthesis STA
Education: Bachelor's or master’s degree in electronics engineering or related field
Job Location: Bangalore, India
We are seeking a highly motivated Synthesis and STA Engineer to join our team. The successful candidate will be responsible for performing Synthesis and STA timing closure for our cutting-edge designs. The ideal candidate will have a strong background in Synthesis STA and experience with industry-standard EDA tools.
Job 1: 6+ years of relevant experience
Requirements:
- Candidate should have strong STA fundamentals
- Has done timing sign-off including timing margin calculations independently on So C Level
- Experience in handling STA of multi-power domain designs
- STA flow enhancement, abstraction with bottleneck identification
- Proficient in design margins and SDC contructs
- TAT reduction in multi-mode, multi power domain/designs
- Generate timing ECOs for Physical design
- Drive ambitious schedules and enables dependent teams to accomplish
- Proficient with EDA tools from Synopsys/Cadence
- Excellent analytical & communication skills
- Show ability to collaborate in a multi-functional environment, cross-site or cross-time zone.
- Proficient in Tcl and Perl or other scripting relevant language is a plus.
Job 2: 8+ years of relevant experience
Requirements:
- Develop and implement high-performance, low-power, and area-efficient digital designs for ASICs and So Cs using industry-standard EDA tools.
- Work closely with design teams to understand the requirements and constraints of the design, and provide feedback on design feasibility, timing and power.
- Debug and resolve design issues related to synthesis, timing, power, and area
- Understanding of DFT flows, including scan insertion and ATPG
- Optimize designs for power, performance, and area, and meet design goals within the given schedule.
- Proficient with EDA tools from Synopsys/Cadence/Mentor
- Excellent analytical and communication skills
- Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone
- Proficient in Tcl and Perl or other scripting relevant languages is a plus.
Working time: Monday - Friday
Contact: Ms. Van Anh – Whats App: +84 935059669
Email:

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