STA/ Synthesis Engineer

2 days ago

bangalore, India UST Full time
Job Description: STA Engineer
Company: UST Global
Location: Bangalore, India
Company Overview:
UST Global is a leading digital technology solutions company that empowers organizations to transform their businesses through cutting-edge technologies. With a global presence across 25 countries, we deliver innovative solutions and services in digital consulting, product engineering, automation, cloud, and cybersecurity. Our mission is to create boundless impact, improve the lives of billions, and build a future where technology and business converge seamlessly.
Position Overview:
We are seeking a highly skilled STA (Static Timing Analysis) Engineer with over 6 years of experience to join our team in Bangalore. The ideal candidate will have strong expertise in STA fundamentals and a proven track record in SOC-level timing sign-off. This role involves working on complex multi-power domain designs, enhancing STA flows, and generating timing ECOs for physical design.
Key Responsibilities:
Static Timing Analysis (STA):
- Demonstrate strong fundamentals in STA.
- Perform SOC-level timing sign-off, including independent timing margin calculations.
Design and Analysis:
- Handle STA for multi-power domain designs.
- Enhance STA flows and perform abstraction with bottleneck identification.
- Generate timing ECOs (Engineering Change Orders) to support physical design.
Design Margins and SDC Constructs:
- Proficiently manage design margins and constraints using SDC (Synopsys Design Constraints) constructs.
EDA Tools Expertise:
- Utilize industry-standard EDA tools from Synopsys and Cadence efficiently.
Qualifications:
- Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field.
- Minimum 6+ years of relevant experience in Static Timing Analysis in complex SOC designs.
- Deep understanding of multi-power domain design and STA methodologies.
- Strong problem-solving skills and ability to enhance existing STA flows.
- Proficiency in Synopsys and Cadence EDA tools.
No. of Positions:
SOC Level - STA Engineer- 10+ Years
SOC Level- Synthesis and Power Analysis Engineer- 8+ Years
STA Engineer- 6+ Years
Preferred Skills:
- Excellent communication and teamwork abilities.
- Experience in generating and managing timing ECOs.
- Familiarity with the latest trends and advancements in STA and physical design methodologies.
Why Join UST Global?
At UST Global, we are committed to fostering an environment that encourages growth, innovation, and teamwork. We offer opportunities for professional development, a culture that values work-life balance, and a chance to work on transformative projects that have a global impact.
If you are passionate about cutting-edge semiconductor design and meet the qualifications, we encourage you to apply.
You can also share your resume to

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