STA/ Synthesis Engineer

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

Job Description: STA Engineer Company: UST Global Location: Bangalore, India Company Overview: UST Global is a leading digital technology solutions company that empowers organizations to transform their businesses through cutting-edge technologies. With a global presence across 25 countries, we deliver innovative solutions and services in...

Job Description: STA Engineer Company: UST Global Location: Bangalore, India Company Overview: UST Global is a leading digital technology solutions company that empowers organizations to transform their businesses through cutting-edge technologies. With a global presence across 25 countries, we deliver innovative solutions and services in...

Job Description: STA EngineerCompany: UST GlobalLocation: Bangalore, IndiaCompany Overview:UST Global is a leading digital technology solutions company that empowers organizations to transform their businesses through cutting-edge technologies. With a global presence across 25 countries, we deliver innovative solutions and services in digital consulting,...

Exp: 3+ yearsLocation: BangaloreShort notice preferredJD: Candidate with 3+ yrs exp in Synthesis/STA roleExperience in handling complex data path-oriented multi-million gate synthesisWorking Knowledge of Physical synthesis using tools like Genus, Fusion CompilerExperience in debugging for multi-clock domains hierarchical/flat timing analysis.Good working...

Exp: 3+ yearsLocation: BangaloreShort notice preferredJD: Candidate with 3+ yrs exp in Synthesis/STA roleExperience in handling complex data path-oriented multi-million gate synthesisWorking Knowledge of Physical synthesis using tools like Genus, Fusion CompilerExperience in debugging for multi-clock domains hierarchical/flat timing analysis.Good working...

Exp: 3+ years Location: Bangalore Short notice preferred JD: Candidate with 3+ yrs exp in Synthesis/STA role Experience in handling complex data path-oriented multi-million gate synthesis Working Knowledge of Physical synthesis using tools like Genus, Fusion Compiler Experience in debugging for multi-clock domains hierarchical/flat timing analysis. Good...

Hi All, Synthesis/STA/DFT (3) JD · Engineering Graduates with MS/MTech/ME (EE/CS/EC) with 5 years or BTech/BS/BE(EE/CS/EC) with 7years in VLSI industry · Hands on experience with RTL Synthesis, STA, Formal verification, and DFT are required; for DFT, expect at least minimum understanding of clocking and reset to scan logic · Must have recent 2-3...

3+ years experience in STA/Synthesis Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis. Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge on the Timing closure on Sub system level & Block level and Chip...

L&T Technology is looking to hire for STA Engineers. Job Location : Bangalore Detailed JD is below :: JD For STA Engineer-6+ ’ experience • Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. • Can work closely with FE team for constraints development and constraints cleanup. •...

Hi,Greetings from ACL Digital,Looking for STA/ Synthesis Engineer: 1. Exp: 3+ years2. Availability: immediate to 30 days3. Experience in Synthesis, STA, Lint, CDC, Spyglass, Formal Verification and good debugging skills.4. CLP/LEC.Interested can share CV to sharmila.b@acldigital.com

Senior STA Engineer Responsibilities: § Hands on responsibility in top level timing constraints generation/debug on complex GPU/SOCs including configuring different timing modes (Func, DFT, JTAG, MBIST, etc). § Work with a team of engineers on timing closure and constraints generation/debug. § Has prior STA & timing closure experience. §...

Hi All,Synthesis/STA/DFT (3) JD· Engineering Graduates with MS/MTech/ME (EE/CS/EC) with 5 years or BTech/BS/BE(EE/CS/EC) with 7years in VLSI industry· Hands on experience with RTL Synthesis, STA, Formal verification, and DFT are required; for DFT, expect at least minimum understanding of clocking and reset to scan logic· Must have recent 2-3 years of...

Senior STA EngineerResponsibilities:§ Hands on responsibility in top level timing constraints generation/debug on complex GPU/SOCs including configuring different timing modes (Func, DFT, JTAG, MBIST, etc).§ Work with a team of engineers on timing closure and constraints generation/debug.§ Has prior STA & timing closure experience.§ Understanding of...

Hi All, Synthesis/STA/DFT (3) JD · Engineering Graduates with MS/MTech/ME (EE/CS/EC) with 5 years or BTech/BS/BE(EE/CS/EC) with 7years in VLSI industry · Hands on experience with RTL Synthesis, STA, Formal verification, and DFT are required; for DFT, expect at least minimum understanding of clocking and reset to scan logic · Must have recent 2-3 years of...

Hi All,Synthesis/STA/DFT (3) JD· Engineering Graduates with MS/MTech/ME (EE/CS/EC) with 5 years or BTech/BS/BE(EE/CS/EC) with 7years in VLSI industry· Hands on experience with RTL Synthesis, STA, Formal verification, and DFT are required; for DFT, expect at least minimum understanding of clocking and reset to scan logic· Must have recent 2-3 years of...

Senior STA EngineerResponsibilities:§ Hands on responsibility in top level timing constraints generation/debug on complex GPU/SOCs including configuring different timing modes (Func, DFT, JTAG, MBIST, etc).§ Work with a team of engineers on timing closure and constraints generation/debug.§ Has prior STA & timing closure experience.§ Understanding of...

Senior STA Engineer Responsibilities: § Hands on responsibility in top level timing constraints generation/debug on complex GPU/SOCs including configuring different timing modes (Func, DFT, JTAG, MBIST, etc). § Work with a team of engineers on timing closure and constraints generation/debug. § Has prior STA & timing closure experience. § Understanding...

We are looking for an STA Engineer in Bangalore for the following role and with the given background/skill sets. Does this sound like a good role for you?.Senior STA/Synthesis Engineer ( Application Engineering - Timing Constraint Manager product)Location: BangaloreExperience: 4+yrs to 8yrsBachelor/Master in EE/CS with 4+ years of relevant...