Senior STA Engineer
2 months ago
Responsibilities:
§ Hands on responsibility in top level timing constraints generation/debug on complex GPU/SOCs including configuring different timing modes (Func, DFT, JTAG, MBIST, etc).
§ Work with a team of engineers on timing closure and constraints generation/debug.
§ Has prior STA & timing closure experience.
§ Understanding of different implementation styles of clock in design and latency/skew.
§ Understanding of clock domain crossings, source synchronous buses, multi-voltage timing.
§ Understanding of timing sign off flow and methodology, timing budgeting, derating and timing across different voltage domains § Working knowledge of special timing checks (Asynchronous, source sync interfaces, etc).
§ Interact with RTL and SOC physical implementation teams to resolve timing issues.
§ Mentoring junior engineers in different areas of timing flows and methodologies § Ability to influence flow and methodology enhancements for improvement § Ability to work independently and influence cross functional teams to make good technical design trade-offs between power, area, timing Skills and Qualifications
Background/Experience:
o 8+ years relevant experience preferred
o Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must
o Understanding and working knowledge of the SOC/ASIC design flow.
o Possesses strong technical qualities and skillsets with good analytical debug skills
o Experience with smaller process nodes is strongly preferred
o Working knowledge and detail understanding of OCV, AOCV & POCV is preferred.
o Strong hands-on experience with industry standard STA tools (Ex. PrimeTime, Tempus)
o Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools an added plus
o Experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs is a plus.
o Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage.
o Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python is preferred.Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to details.
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