Digital Design Engineer

ACL Digital hiring for below position! ASIC Design Engineer Job Description Must have proven track record of ASIC design on several production tape-outs. Experience in Designing RTL block for an SOC. Experience in integrating ASIC IP into an SOC. Experience with Arm architecture and APB, AXI, CHI protocols. Experience with synthesis, static timing...

ACL Digital hiring for below position ASIC Design Engineer Job Description Must have proven track record of ASIC design on several production tape-outs. Experience in Designing RTL block for an SOC. Experience in integrating ASIC IP into an SOC. Experience with Arm architecture and APB, AXI, CHI protocols. Experience with synthesis, static timing...

RTL Design Engineer Experience : 2-3 years Location : Hyderabad Knowledge in RTL Coding in Verilog or VHDL Strong understanding of Logic design, Digital design, System design aspects, FPGA flow, Design Constraints etc. Knowledge in Xilinx FPGA architecture and design flows like IPI, XDC etc. Good Knowledge in Tcl, Python scripting Interested,please...

ACL Digital hiring for below position!???????????????? ???????????????????????? ???????????????????????????????????????????? ????????????????????????????????????????????▪️ Must have proven track record of ASIC design on several production tape-outs. ▪️ Experience in Designing RTL block for an SOC. ▪️ Experience in integrating ASIC IP into an...

Exp level:4+ years Location: Hyderabad/Banglaore Job Title:FPGA Engineer Required skill for the Job:• Basic STA knowledge along with tools like Vivado. • Experience on FPGA platforms like AMD(XILINX)/Altera. • Expertise in digital hardware designing using Verilog on large AMD(Xilinx)/altera FPGAs • Experience in scripting language like perl,...

RTL Design EngineerExperience : 2-3 yearsLocation : HyderabadKnowledge in RTL Coding in Verilog or VHDLStrong understanding of Logic design, Digital design, System design aspects, FPGA flow, Design Constraints etc.Knowledge in Xilinx FPGA architecture and design flows like IPI, XDC etc.Good Knowledge in Tcl, Python scriptingInterested,please drop your...

RTL Design EngineerExperience : 2-3 yearsLocation : HyderabadKnowledge in RTL Coding in Verilog or VHDLStrong understanding of Logic design, Digital design, System design aspects, FPGA flow, Design Constraints etc.Knowledge in Xilinx FPGA architecture and design flows like IPI, XDC etc.Good Knowledge in Tcl, Python scriptingInterested,please drop your...

RTL Design Engineer Experience : 2-3 years Location : Hyderabad Knowledge in RTL Coding in Verilog or VHDL Strong understanding of Logic design, Digital design, System design aspects, FPGA flow, Design Constraints etc. Knowledge in Xilinx FPGA architecture and design flows like IPI, XDC etc. Good Knowledge in Tcl, Python scripting Interested,please drop...

Exp level:4+ yearsLocation: Hyderabad/BanglaoreJob Title:FPGA EngineerRequired skill for the Job:• Basic STA knowledge along with tools like Vivado.• Experience on FPGA platforms like AMD(XILINX)/Altera.• Expertise in digital hardware designing using Verilog on large AMD(Xilinx)/altera FPGAs• Experience in scripting language like perl, python and...

ACL Digital hiring for below position! 𝗔𝗦𝗜𝗖 𝗗𝗲𝘀𝗶𝗴𝗻 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿 𝗝𝗼𝗯 𝗗𝗲𝘀𝗰𝗿𝗶𝗽𝘁𝗶𝗼𝗻 ▪️ Must have proven track record of ASIC design on several production tape-outs. ▪️ Experience in Designing RTL block for an SOC. ▪️ Experience in integrating ASIC IP into...