RTL Design Engineer

2 weeks ago

Hyderabad, India ACL Digital Full time

Job Title: RTL Design EngineersExp Level: 2-3 yrsLoctaion: HyderabadJob Description:- Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog.- Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams.- Requires strong fundamentals in digital design, timing closure, and understanding of the ASIC flow.- You'll debug simulation failures, implement ECOs, and support gate-level simulations.- Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tapeout goals.- Bachelor's or Master's degree in engineering in EE/CS is essential, along with 2-3 years of relevant experience.Share resumes to

  • RTL Design Engineer

    3 weeks ago

    Hyderabad, India ACL Digital Full time

    Job Title: RTL Design Engineers Exp Level: 4+ yrsLoctaion: HyderabadJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• SoC & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...

  • RTL Design Engineer

    3 weeks ago

    Hyderabad, India ACL Digital Full time

    Job Title: RTL Design Engineers Exp Level: 4+ yrsLoctaion: Hyderabad /BangaloreJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• SoC & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...

  • Rtl design engineer

    6 days ago

    Hyderabad, India ACL Digital Full time

    Job Title: RTL Design Engineers Exp Level: 4+ yrsLoctaion: HyderabadJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• So C & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...

  • Rtl design engineer

    5 days ago

    Hyderabad, India ACL Digital Full time

    Job Title: RTL Design Engineers Exp Level: 4+ yrsLoctaion: HyderabadJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• So C & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...

  • RTL Design Engineer

    3 days ago

    Hyderabad, Telangana, India ACL Digital Full time ₹ 4,00,000 - ₹ 12,00,000 per year

    RTL Design EngineerSkill: ASIC RTL Design with LINT, CDC. Experience: 1 to 3 Years Notice Period: Immediate to 15 days Share your updated resume now.

  • RTL Design Engineer

    7 days ago

    Hyderabad, India ACL Digital Full time

    Job Title - RTL Design Engineers Exp Level: 4+ yrsLoctaion: Hyderabad /BangaloreJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• SoC & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL...

  • RTL Design Engineer

    3 weeks ago

    Hyderabad, India ACL Digital Full time

    Position: RTL Design Engineer Experience: 5 - 8 Years Qualifications: BE/Btech in ECE/EEE Responsibilities - The candidate should have strong RTL design experience. Strong design experience in Ethernet IPs or Ethernet protocol domain. Knowledge in Verilog/VHDL languages Scripting languages: TCL/Perl/Python (any one). Knowledge of AXI Protocols.

  • RTL Design Engineer

    2 weeks ago

    Hyderabad, India ACL Digital Full time

    Position: RTL Design Engineer Experience: 5 - 8 Years Qualifications: BE/Btech in ECE/EEE Responsibilities - The candidate should have strong RTL design experience. Strong design experience in Ethernet IPs or Ethernet protocol domain. Knowledge in Verilog/VHDL languages Scripting languages: TCL/Perl/Python (any one). Knowledge of AXI Protocols.

  • RTL Design Engineer

    2 weeks ago

    Hyderabad, India ACL Digital Full time

    Position: RTL Design Engineer Experience: 5 - 8 Years Qualifications: BE/Btech in ECE/EEE Responsibilities - - The candidate should have strong RTL design experience. - Strong design experience in Ethernet IPs or Ethernet protocol domain. - Knowledge in Verilog/VHDL languages - Scripting languages: TCL/Perl/Python (any one). - Knowledge of AXI Protocols.

  • RTL Design Engineer

    4 days ago

    Hyderabad, India ACL Digital Full time

    Position: RTL Design Engineer Experience: 5 - 8 Years Qualifications: BE/Btech in ECE/EEE Responsibilities - The candidate should have strong RTL design experience. Strong design experience in Ethernet IPs or Ethernet protocol domain. Knowledge in Verilog/VHDL languages Scripting languages: TCL/Perl/Python (any one). Knowledge of AXI Protocols.