Digital Logic Design Engineer
3 days ago
Job Title: RTL Design EngineersExp Level: 2-3 yrsLoctaion: Hyderabad Job Description:Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog. Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams. Requires strong fundamentals in digital design, timing closure, and understanding of the ASIC flow. You'll debug simulation failures, implement ECOs, and support gate-level simulations. Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tapeout goals. Bachelor's or Master's degree in engineering in EE/CS is essential, along with 2-3 years of relevant experience.Share resumes to raksha.k@acldigital.com
-
Senior Principal Logic Design Engineer
2 weeks ago
Hyderabad, India Mulya Technologies Full timeSenior Principal Logic Design Engineer Location: BangaloreWe are a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processingAs a SPE Logic Design Engineer, you’ll play a pivotal role in designing and implementing the world’s best...
-
RTL Design Engineer
4 days ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design Engineers Exp Level: 2-3 yrsLoctaion: HyderabadJob Description:Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog .Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams.Requires strong...
-
RTL Design Engineer
3 days ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design Engineers Exp Level: 2-3 yrs Loctaion: Hyderabad Job Description: Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog . Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams. Requires strong fundamentals in...
-
RTL Design Engineer
1 day ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design Engineers Exp Level: 2-3 yrs Loctaion: Hyderabad Job Description: - Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog. - Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams. - Requires strong fundamentals in...
-
RTL Design Engineer
5 days ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design EngineersExp Level: 2-3 yrsLoctaion: HyderabadJob Description:Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog .Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams.Requires strong fundamentals in digital...
-
RTL Design Engineer
2 days ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design EngineersExp Level: 2-3 yrsLoctaion: HyderabadJob Description:Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog .Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams.Requires strong fundamentals in digital...
-
RTL Design Engineer
5 days ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design Engineers Exp Level: 2-3 yrs Loctaion: Hyderabad Job Description: 1. Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog. 2. Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams. 3. Requires strong fundamentals in...
-
RTL Design Engineer
4 days ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design EngineersExp Level: 2-3 yrsLoctaion: Hyderabad Job Description:Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog. Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams. Requires strong fundamentals in digital...
-
RTL Design Engineer
1 day ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design EngineersExp Level: 2-3 yrsLoctaion: Hyderabad Job Description:Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog. Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams. Requires strong fundamentals in digital...
-
RTL Design Engineer
1 day ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design EngineersExp Level: 2-3 yrsLoctaion: HyderabadJob Description:- Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog.- Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams.- Requires strong fundamentals in digital...
