PD - Frontend Synthesis

Hi All,We are looking for PD(Front-end Synthesis) Engineers/Leads.Fullchip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package designFullchip timing - PrimeTime constraints, clocks.Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains.Voltage Island - Coarse level UPF/ Clock...

Hi All, We are looking for PD(Front-end Synthesis ) Engineers/Leads. Fullchip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package design Fullchip timing - Prime Time constraints, clocks. Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains. Voltage Island - Coarse...

Hi All,We are looking for PD(Front-end Synthesis ) Engineers/Leads.Fullchip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package designFullchip timing - PrimeTime constraints, clocks.Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains.Voltage Island - Coarse level UPF/ Clock...

Hi All,We are looking for PD(Front-end Synthesis) Engineers/Leads.Fullchip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package designFullchip timing - PrimeTime constraints, clocks.Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains.Voltage Island - Coarse level UPF/ Clock...

Hi All, We are looking for PD(Front-end Synthesis ) Engineers/Leads. Fullchip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package design Fullchip timing - PrimeTime constraints, clocks. Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains. Voltage Island - Coarse level UPF/...

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

3+ years experience in STA/Synthesis Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis. Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge on the Timing closure on Sub system level & Block level and Chip...

Exp: 3+ years Location: Bangalore Short notice preferred JD: Candidate with 3+ yrs exp in Synthesis/STA role Experience in handling complex data path-oriented multi-million gate synthesis Working Knowledge of Physical synthesis using tools like Genus, Fusion Compiler Experience in debugging for multi-clock domains hierarchical/flat timing analysis. Good...

Exp: 3+ yearsLocation: BangaloreShort notice preferredJD: Candidate with 3+ yrs exp in Synthesis/STA roleExperience in handling complex data path-oriented multi-million gate synthesisWorking Knowledge of Physical synthesis using tools like Genus, Fusion CompilerExperience in debugging for multi-clock domains hierarchical/flat timing analysis.Good working...

3+ years experience in STA/Synthesis Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis. Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge on the Timing closure on Sub system level & Block level and Chip...

Exp: 3+ yearsLocation: BangaloreShort notice preferredJD: Candidate with 3+ yrs exp in Synthesis/STA roleExperience in handling complex data path-oriented multi-million gate synthesisWorking Knowledge of Physical synthesis using tools like Genus, Fusion CompilerExperience in debugging for multi-clock domains hierarchical/flat timing analysis.Good working...

Exp: 3+ years Location: Bangalore Short notice preferred JD: Candidate with 3+ yrs exp in Synthesis/STA role Experience in handling complex data path-oriented multi-million gate synthesis Working Knowledge of Physical synthesis using tools like Genus, Fusion Compiler Experience in debugging for multi-clock domains hierarchical/flat timing analysis. Good...

ACL Digital is hiring for PD and STA Engineers for Bangalore and Location. 3+years of experience in Physical Design. Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure. Notice period- Immediate to 30 days

ACL Digital is hiring for PD and STA Engineers for Bangalore and Location.3+years of experience in Physical Design.Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.Notice period- Immediate to 30 days

LTTS is hiring for Physical Design Engineers with 5+ Years of experience. Job Location : Bangalore, India Job description is as below :: Top 5 Required Skills/Mandatory skills 1. Synthesis 2. Constraints Management 3. Logic Equivalence Check 4. CLP 5. STA Required Education: Bachelor's degree in Computer Science, Electrical/Electronics Engineering,...

LTTS is hiring for Physical Design Engineers with 5+ Years of experience. Job Location : Bangalore, India Job description is as below :: Top 5 Required Skills/Mandatory skills 1. Synthesis 2. Constraints Management 3. Logic Equivalence Check 4. CLP 5. STA Required Education: Bachelor's degree in Computer Science,...

ACL Digital is hiring for PD and STA Engineers for Bangalore and Location.3+years of experience in Physical Design.Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.Notice period- Immediate to 30 days

Role : PD Lead Exp : 7+ years Location : Bangalore BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2 GDS flow is desired Should be able to handle Full chip Pn R (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep...