Senior Physical Design Engineer

Responsibilities :  Develop and support automated physical design (PD) CAD flows, including floorplanning, placement, and routing optimization.  Customize and optimize physical design flows using industry-standard EDA tools (such as Synopsys ICC2, Cadence Innovus).  Collaborate with the design and CAD teams to improve PD workflows,...

Responsibilities :  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and area targets.  Perform efficient Clock planning and...

Responsibilities :  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and area targets.  Perform efficient Clock planning and...

Responsibilities : Minimum 8+ years of experience and with 0 - 30 Notice period Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for HighSpeed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and areatargets. Perform efficient Clock planning and distribution to...

Responsibilities:  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for HighSpeed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and areatargets.  Perform efficient Clock planning and distribution to...

Responsibilities :  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and area targets.  Perform efficient Clock planning and...

Job Role: Physical Design Engineer- Senior/Lead Location: Bangalore, Hyderabad, Noida and Ahmedabad Experience Required: 5+ ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal...

Minimum 15+ Years of experience So C Physical Design. Skills – have working experience in advanced Fin FET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys Pn R/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin...

Senior Physical Design Engineer: Exp-6+yrs KEY RESPONSIBILITIES: Lead the team responsible for Synthesis, Physical Design, timing and Physical closure Manage a large team of internal and external resources Responsible for ensuring the completion of the SOC chip on schedule with high QOR Physical implementation of block level and subsystem...

Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 5+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power...

Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 5+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power...

Minimum 15+ Years of experience SoC Physical Design.Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm.Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must.This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments...

Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 5+ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity,...

Physical Design Manager / Senior Principal Physical Design Engineer Bangalore Our main business focuses on automotive microcontrollers and So Cs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. We will continue to integrate the latest electronic and...

Senior Physical Design Engineer: Exp-6+yrs KEY RESPONSIBILITIES: Lead the team responsible for Synthesis, Physical Design, timing and Physical closure Manage a large team of internal and external resources Responsible for ensuring the completion of the SOC chip on schedule with high QOR Physical implementation of block level and subsystem...

Dear Leads in PD VLSI world , We are TA team working towards finding Senior Talent in PD. Please feel free to visit - LTTS has constantly helped enterprises thrive in the new era of the digital revolution with over 650 engineers and expertise in all types of Nodes. We have also been named the only Semiconductor Pure-Play Engineering Services Leader....

We need an experienced Physical Design Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/So C chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements 1 - 2 Years of experience in physical design Bachelor’s or master’s...

Job Title: Physical Design Engineer Location: Bangalore/ Hyderabad Job Summary: We are seeking a skilled and detail-oriented Physical Design Engineer to work on the physical implementation of complex ASICs and So Cs. The role involves performing various backend design tasks, including floorplanning, placement, routing, timing closure, and power...

PNR Lead Engineers Work Location : Bangalore and Hyderabad Experience: 3 Years to 8 Years Technical Skills: Should be able to handle Full chip Pn R (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, ...

e Infochips (An Arrow Company) Hiring Physical Design Engineer Experience - 4+ Years Location- Bangalore/Hyderabad/Ahmedabad/Noida/Chennai Job description is as below: * Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII, * Block level Physical Signoff, * Block level Timing Signoff and ECO generation. * Block level...