Senior physical design engineer

3 weeks ago


Bangalore, India Modernize Chip Solutions Full time

Minimum 15+ Years of experience So C Physical Design. Skills – have working experience in advanced Fin FET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys Pn R/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments /Feed through/ LFU Optimization/ Work hands-on to solve critical design and execution issues related to physical verification/implementation and sign-off. Expertise : Strong hands-on experience with Chip Level / Sub-chip level floor planning, Performing floor-planning and routing studies and implementation at block and full-chip level Push down the top-level floorplan and clock to Partition. partition, pin assignment, Power planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps. Closely working with Package team and reaching Die file milestones Location- Hyd/BLR Availability- Immediate to 60 days.



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