PD - Frontend Synthesis

Hi All,We are looking for PD(Front-end Synthesis) Engineers/Leads.Fullchip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package designFullchip timing - PrimeTime constraints, clocks.Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains.Voltage Island - Coarse level UPF/ Clock...

Hi All, We are looking for PD(Front-end Synthesis ) Engineers/Leads. Fullchip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package design Fullchip timing - PrimeTime constraints, clocks. Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains. Voltage Island - Coarse level UPF/...

Hi All,We are looking for PD(Front-end Synthesis ) Engineers/Leads.Fullchip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package designFullchip timing - PrimeTime constraints, clocks.Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains.Voltage Island - Coarse level UPF/ Clock...

Dear Leads in PD VLSI world ,We are TA team working towards finding Senior Talent in PD.Please feel free to visit - has constantly helped enterprises thrive in the new era of the digital revolution with over 650 engineers and expertise in all types of Nodes. We have also been named the only Semiconductor Pure-Play Engineering Services Leader. For decades,...

Dear Leads in PD VLSI world , We are TA team working towards finding Senior Talent in PD. Please feel free to visit - LTTS has constantly helped enterprises thrive in the new era of the digital revolution with over 650 engineers and expertise in all types of Nodes. We have also been named the only Semiconductor Pure-Play Engineering Services Leader....

Exp: 3+ yearsLocation: BangaloreShort notice preferredJD: Candidate with 3+ yrs exp in Synthesis/STA roleExperience in handling complex data path-oriented multi-million gate synthesisWorking Knowledge of Physical synthesis using tools like Genus, Fusion CompilerExperience in debugging for multi-clock domains hierarchical/flat timing analysis.Good working...

Exp: 3+ yearsLocation: BangaloreShort notice preferredJD: Candidate with 3+ yrs exp in Synthesis/STA roleExperience in handling complex data path-oriented multi-million gate synthesisWorking Knowledge of Physical synthesis using tools like Genus, Fusion CompilerExperience in debugging for multi-clock domains hierarchical/flat timing analysis.Good working...

Exp: 3+ years Location: Bangalore Short notice preferred JD: Candidate with 3+ yrs exp in Synthesis/STA role Experience in handling complex data path-oriented multi-million gate synthesis Working Knowledge of Physical synthesis using tools like Genus, Fusion Compiler Experience in debugging for multi-clock domains hierarchical/flat timing analysis. Good...

ACL Digital is hiring for PD and STA Engineers for Bangalore and Location. 3+years of experience in Physical Design. Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure. Notice period- Immediate to 30 days

ACL Digital is hiring for PD and STA Engineers for Bangalore and Location.3+years of experience in Physical Design.Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.Notice period- Immediate to 30 days

LTTS is hiring for Physical Design Engineers with 5+ Years of experience. Job Location : Bangalore, India Job description is as below :: Top 5 Required Skills/Mandatory skills 1. Synthesis 2. Constraints Management 3. Logic Equivalence Check 4. CLP 5. STA Required Education: Bachelor's degree in Computer Science,...

ACL Digital is hiring for PD and STA Engineers for Bangalore and Location.3+years of experience in Physical Design.Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.Notice period- Immediate to 30 days

Role : PD Lead Exp : 7+ years Location : Bangalore BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2 GDS flow is desired Should be able to handle Full chip Pn R (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep...

Role : PD Lead Exp : 7+ years Location : Bangalore BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desired Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep...

Responsibilities :  Develop and support automated physical design (PD) CAD flows, including floorplanning, placement, and routing optimization.  Customize and optimize physical design flows using industry-standard EDA tools (such as Synopsys ICC2, Cadence Innovus).  Collaborate with the design and CAD teams to improve PD workflows,...

Role: PD LeadExperience: 7+yrsLocation: BangaloreTechnical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for...

Role : PD LeadExp : 7+ yearsLocation : BangaloreBE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical DesignDetailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desiredShould be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage designDeep understanding...

Role : PD Lead Exp : 7+ years Location : Bangalore BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desired Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep...

LTTS is hiring for Physical Design Engineers with 5+ Years of experience. Job Location : Bangalore, IndiaJob description is as below ::Top 5 Required Skills/Mandatory skills 1. Synthesis 2. Constraints Management 3. Logic Equivalence Check 4. CLP 5. STA Required Education: Bachelor's degree in Computer Science, Electrical/Electronics Engineering,...

Role : PD LeadExp : 7+ yearsLocation : BangaloreBE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical DesignDetailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desiredShould be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage designDeep understanding...