PD - Frontend Synthesis

Hi All,We are looking for PD(Front-end Synthesis) Engineers/Leads.Fullchip rollup, Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package designFullchip timing PrimeTime constraints, clocks.Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains.Voltage Island Coarse level UPF/ Clock gating.Exp:...

Title: PD(Synthesis) EngineerDescriptionFull chip rollup, Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package designFull chip timing Primetime constraints, clocks.Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains.Voltage Island Coarse level UPF/ Clock gating.

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

Below are the open positions!!!STA : 4+ YearsExperience in chiptop / Top Level / Block level / Fullchip /#Tweaker #Tempus#Primetime#PDN / #IR_Drop / #EMIR : 3+ Yrs> Voltas, Redhawk_SC, EMIR, Power integrityPhysical Design: 4+ YrsExperience in Block level / Full chip /Top Level#Innovus #ICC2Synthesis: 3+ Yrs.Experience in Core Synthesis#Genus #Fusion...

Title: #PDCAD EngineersLocation: Hyderabad and BangaloreDescription:Physical Design Implementation Signoff closure, Development and support of ASIC implementation / PNR CAD flows.CAD flow regressions/releaseRTL2GDSII PD flows development experience (SNPS & CDNS tool suite)PD tool (SNPS based both construction & sign-off)Understand sign-off reports,...

We are looking for a Physical Design Engineer with exposure to Low Power Design. Experience in ASIC FLOW in various stages like SYNTHESIS & PD. Handle block level and Top level CLP/VCLP. Experience in CLP/VCLP and Low-power Design implementation. Debugging skills over UPF/LP and MV issues till Tapeout. Validation of UPF before PD implementation and...

Job Description Provide technical and managerial Leadership to a PD team for a SoC Chip development owning partitions and full-chip from synthesis to place and route through all sign-off including timing signoff, physical verification, EMIR signoff, and formal verification. Influence tools, flows, and overall design methodology in design...

Overview Microsoft’s Azure Hardware Systems and Infrastructure team are at the forefront of the technology revolution, driving the development and deployment of cutting-edge cloud infrastructure solutions. Within our Silicon Engineering team, you will have the opportunity to work with some of the brightest minds in the industry to help shape the...

Overview Microsoft’s Cloud Compute Development Organization (CCDO) is seeking passionate, driven and intellectually curious engineers to join our silicon hardware physical design team, covering RTL to GDS methodology, design convergence, and design quality for our projects. We are responsible for delivering cutting-edge, custom IP and SOC designs...

Our client provides end to end semiconductor design services covering digital, analog, system design & embedded software. They are poised to be the fastest growing semiconductor services company.They are looking for STA Engineer to be based at Bangalore and Noida with the following : - Ideal candidate will have 4 to 10 years of experience in field of...

Our client provides end to end semiconductor design services covering digital, analog, system design & embedded software. They are poised to be the fastest growing semiconductor services company.They are looking for STA Engineer to be based at Bangalore and Noida with the following : - Ideal candidate will have 4 to 10 years of experience in field of...

Position : Senior PD Engineer ADI's Digital Business Unit (DBU) is looking for Senior PD Engineer for the development of complex mixed Signal SoCs. These chips are manufactured in most leading edge process nodes and high speed clock rates. These SoCs involve multiple processor cores and speed signal processing hardware running at high speed.  ...

Position : Senior PD Engineer ADI's Digital Business Unit (DBU) is looking for Senior PD Engineer for the development of complex mixed Signal SoCs. These chips are manufactured in most leading edge process nodes and high speed clock rates. These SoCs involve multiple processor cores and speed signal processing hardware running at high speed.  ...

ACL Digital is hiring for PD and STA Engineers for Bangalore and Hyderabad Locations.3+years experience in Physical Design.Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.

ACL Digital is hiring for PD and STA Engineers for Bangalore and Hyderabad Locations.3+years experience in Physical Design.Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.

Role : RTL Design LeadLocation : Bangalore, Hyderabad, Chennai, Ahmadabad, Pune.Experience : 10-15 YearsMust Haves :- 10-15 years of proven experience in ASIC design and SoC integration.- Knowledge in linting and CDC analysis.- Good knowledge of PCIe, HBM, and Processor subsystem integration.- Expertise in managing constraints updation (IP to SoC level),...

Role : RTL Design LeadLocation : Bangalore, Hyderabad, Chennai, Ahmadabad, Pune.Experience : 10-15 YearsMust Haves :- 10-15 years of proven experience in ASIC design and SoC integration.- Knowledge in linting and CDC analysis.- Good knowledge of PCIe, HBM, and Processor subsystem integration.- Expertise in managing constraints updation (IP to SoC level),...

Role : RTL Design LeadLocation : Bangalore, Hyderabad, Chennai, Ahmadabad, Pune.Experience : 10-15 YearsMust Haves :- 10-15 years of proven experience in ASIC design and SoC integration.- Knowledge in linting and CDC analysis.- Good knowledge of PCIe, HBM, and Processor subsystem integration.- Expertise in managing constraints updation (IP to SoC level),...