RTL Design Lead
2 months ago
Role : RTL Design Lead
Location : Bangalore, Hyderabad, Chennai, Ahmadabad, Pune.
Experience : 10-15 Years
Must Haves :
- 10-15 years of proven experience in ASIC design and SoC integration.
- Knowledge in linting and CDC analysis.
- Good knowledge of PCIe, HBM, and Processor subsystem integration.
- Expertise in managing constraints updation (IP to SoC level), Synthesis and timing analysis.
- Experience in providing PD support.
Job Description :
- 10-15 years of proven experience in ASIC design and SoC integration, with a track record of successful project deliveries.
- Good knowledge of PCIe, HBM, and Processor subsystem integration, demonstrating the ability to address challenges and optimize performance.
- Good knowledge in linting and CDC analysis to ensure code quality and mitigate clock domain crossing issues.
- Expertise in managing constraints updation (IP to SoC level), Synthesis and timing analysis.
- Experience in providing PD support.
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