Lead analysis engineer

2 days ago

Bangalore, India Tessolve Full time

With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolves design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5 G, mm Wave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolves Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities. Tessolves clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. We are seeking a highly skilled and experienced Lead STA (Static Timing Analysis) Engineer to join our team in Bangalore. The ideal candidate will have deep expertise in timing closure for high-speed designs and hands-on experience with Synopsys timing tools. Lead STA efforts for complex So C designs at advanced nodes (3nm and below)Perform timing analysis and closure using Synopsys Prime Time and Fusion Compiler Collaborate with design, physical implementation, and verification teams to resolve timing issues Ensure timing sign-off quality and compliance with project requirements Required Skills & Experience: 8–12 years of experience in Static Timing Analysis Proven experience in high-speed SERDES designs (GHz+ frequencies)Solid understanding of digital design, timing constraints, and physical design flow

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