
Lead Design Analysis Engineer
2 days ago
# ;# ;# ;# ;# ;# ;# ;# ;# ;# ;# ;# ;# ;# ;# ;# ;:
As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA.
# ;# ;# ;# ;# ;# ;# ;# ; # ;# ;# ;# ;# ;# ; # ;# ;# ; # ;# ;# ;# ;# ;# ;# ;# ;# ;# ; :
# ; Understanding of computer architecture and concepts.
# ; Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations.
# ; Good experience in design verification: Sense amplifier analysis, self-time analysis and marginality analysis.
# ; Understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits.
# ; Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.
# ; Strong knowledge of physical implementation impact on circuit performance.
# ; Good understanding of high-performance and low power circuit designs with exposure to FinFet technologies, bitcell stability analysis
# ; Proven experience as the designated responsible individual for a memory design, leading a small team of designer.
# ;# ;# ;# ;# ;# ;# ;# ; # ;# ; # ;# ;# ;# ; # ;# ;# ;# ; # ;# ;# ;# ;# ;# ;# ;# ;# ;# ;# ;# ;# ; # ;# ;# ;# ;# ;# ;.
# ; Circuit Design: Design and develop digital circuits for memory blocks like SRAM, register files, and caches.
# ; Simulation and Verification: Perform simulations and verification to ensure functionality and optimize for power, performance, area, timing, and yield.
# ; Minimum 7 Yrs of experience in SRAM / memory design Margin, Char and its related quality checks.
# ;# ;# ;# ; # ;# ; # ;# ;# ;# ; # ;# ;# ;# ;# ;# ; # ;# ;# ; # ;# ;# ;# ;# ;# ;# ;# ;# ;# ; :
# ; Some Experience of working on Cadence or Synopsys flows.
# ; Experience with Circuit Simulation and Optimization of standard cells.
# ;# ;# ;# ;# ;# ;# ;# ;# ;# ;: # ; # ;# ; # ;# ; # ;# ;# ;# ;# ;
# ;# ;# ;# ;# ;# ; # ;# ;# ;# ;# ;# ;: # ;# ; # ;# ; # ;# ; # ;# ;# ;# ;
# ;# ;# ;# ;# ;# ;# ;# ;: # ;# ;# ;# ;# ;# ;# ;# ;# ;
# ;# ;# ;# ;# ; # ;# ;# ;# ;# ;# ;# ;
ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.
-
Verification Lead Design Engineer
3 weeks ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer. 5+ years of Design Verification experience with SV/UVM Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. Design Verification experience verifying complex designs...
-
Verification Lead Design Engineer
1 week ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...
-
Verification Lead Design Engineer
1 week ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...
-
Sr Principal RTL Design Engineer
2 weeks ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer EngineeringExp- 7-15 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...
-
RTL Release Principal Design Engineer
2 weeks ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer Engineering Exp- 7-12 Yrs - Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc. - Ability to debug existing Verilog/System verilog test cases with little or no help from the designer. - Functional...
-
RTL Release Principal Design Engineer
2 weeks ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer EngineeringExp- 7-12 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...
-
Sr Principal RTL Design Engineer
3 weeks ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer Engineering Exp- 7-15 Yrs - Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc. - Ability to debug existing Verilog/System verilog test cases with little or no help from the designer. - Functional...
-
Sr Principal RTL Design Engineer
7 days ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer EngineeringExp- 7-15 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...
-
Sr Principal RTL Design Engineer
1 week ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer EngineeringExp- 7-15 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...
-
RTL Release Principal Design Engineer
4 weeks ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer EngineeringExp- 7-12 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...