Lead design analysis engineer

4 days ago

Bangalore, India ACL Digital Full time

Job Title: Lead Memory Design Engineer Experience: 6+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / VLSI / Memory IP / So C Job Summary: We are looking for an experienced and highly motivated Lead Memory Design Engineer to drive the architecture, design, and development of advanced memory IPs such as SRAMs, ROMs, CAMs, and Register Files. The role involves leading a team of designers, interacting with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Key Responsibilities: Define architecture and design specifications for custom memory IPs or memory compilers. Design and optimize circuits such as: Memory cell arrays, sense amplifiers, precharge, write drivers, decoders, control logic Lead the schematic-level design and simulation (pre-layout and post-layout) for performance, power, and robustness. Collaborate with layout, verification, and technology teams to ensure full-cycle delivery. Guide post-layout activities including parasitic extraction, IR/EM analysis, and corner validation. Ensure designs meet requirements for DFM, yield, reliability, and aging. Contribute to methodology and flow development for memory design and characterization. Support silicon bring-up and correlation with pre-silicon simulation. Provide technical leadership and mentorship to junior engineers. Drive design reviews and coordinate with program managers for delivery timelines. Required Skills and Experience: ~ B. E/B. Tech or M. E/M. Tech in Electronics, Electrical, or VLSI Engineering. ~8+ years of experience in full-custom memory design (SRAM, ROM, CAM, Register Files). ~ Solid understanding of CMOS analog/digital circuit design principles. ~ Expertise in circuit simulation tools: Spectre, HSPICE, Fast SPICE (XA, Fine Sim, etc.). ~ Experience with advanced nodes (28nm, 16nm, 7nm, 5nm, Fin FET). ~ Hands-on experience with variation analysis (Monte Carlo, PVT), IR drop, and EM checks. ~ Familiarity with memory characterization, yield analysis, and silicon debug. ~ Strong analytical, communication, and leadership skills. Preferred Qualifications: Experience in memory compiler design and automation. Knowledge of low-power memory design techniques (multi-Vt, multi-Vdd, power gating). Experience with ECC, redundancy, and repair strategies. Familiarity with ISO 26262/Safety compliance (for automotive memory IPs). Scripting knowledge (Python, Perl, Tcl) for automation of design and simulation flows. Interested can share Cv to

  • Verification Lead Design Engineer

    5 days ago

    bangalore, India Cadence System Design and Analysis Full time

    BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...

  • Sr Principal PD Design Engineer

    9 hours ago

    Bangalore, India Cadence System Design and Analysis Full time

    This is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on latest Tech. nodes. Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing,...

  • Lead Design Analysis Engineer

    6 days ago

    Bangalore, India ACL Digital Full time

    &## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding...

  • Sr Principal PD Design Engineer

    5 days ago

    bangalore district, India Cadence System Design and Analysis Full time

    This is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on latest Tech. nodes. Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing,...

  • Principal dft design engineer

    4 days ago

    Bangalore, India Cadence System Design And Analysis Full time

    College education in Electronics Engineering or Computer Engineering Exp- 7-12 Yrs - Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc. - Ability to debug existing Verilog/System verilog test cases with little or no help from the designer. - Functional...

  • RTL Release Principal Design Engineer

    6 days ago

    bangalore, India Cadence System Design and Analysis Full time

    College education in Electronics Engineering or Computer Engineering Exp- 7-12 Yrs - Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc. - Ability to debug existing Verilog/System verilog test cases with little or no help from the designer. - Functional...

  • Rtl release principal design engineer

    3 weeks ago

    Bangalore, India Cadence System Design And Analysis Full time

    College education in Electronics Engineering or Computer Engineering Exp- 7-12 Yrs - Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc. - Ability to debug existing Verilog/System verilog test cases with little or no help from the designer. - Functional...

  • Sr Principal RTL Design Engineer

    2 weeks ago

    bangalore, India Cadence System Design and Analysis Full time

    College education in Electronics Engineering or Computer EngineeringExp- 7-15 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...

  • RTL Release Principal Design Engineer

    5 days ago

    bangalore, India Cadence System Design and Analysis Full time

    College education in Electronics Engineering or Computer EngineeringExp- 7-12 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...

  • Lead analysis engineer

    2 days ago

    Bangalore, India Tessolve Full time

    With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolves design services include solutions on advanced process nodes with a healthy eco-system...