SOC DFT Engineer

1 week ago


Bangalore, India ACL Digital Full time

SoC DFT Engineer Job Description: Scan insertion. SCAN DRC/Coverage debug. ATPG Pattern generation. Gate level simulations ( Zero delay/Timing Delay simulations). Worked on JTAG/P1500 protocols. Perl/Tcl scripting. Timing/Formal verification/PD flow knowledge is plus. Location: Bangalore Notice Period: Immediate Experience: 5+ Years


  • SOC DFT Engineer

    2 days ago


    bangalore district, India ACL Digital Full time

    SoC DFT Engineer Job Description: Scan insertion. SCAN DRC/Coverage debug. ATPG Pattern generation. Gate level simulations ( Zero delay/Timing Delay simulations). Worked on JTAG/P1500 protocols. Perl/Tcl scripting. Timing/Formal verification/PD flow knowledge is plus. Location: Bangalore Notice Period: Immediate Experience: 5+ Years

  • SOC DFT Engineer

    2 weeks ago


    bangalore, India ACL Digital Full time

    SoC DFT EngineerJob Description:Scan insertion.SCAN DRC/Coverage debug.ATPG Pattern generation.Gate level simulations ( Zero delay/Timing Delay simulations).Worked on JTAG/P1500 protocols.Perl/Tcl scripting.Timing/Formal verification/PD flow knowledge is plus.Location: BangaloreNotice Period: ImmediateExperience: 5+ Years

  • Lead DFT Engineer

    1 week ago


    bangalore, India ACL Digital Full time

    Job Title: Lead DFT EngineerExperience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC DesignJob Summary:We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with...

  • Lead DFT Engineer

    2 days ago


    bangalore, India ACL Digital Full time

    Job Title: Lead DFT Engineer Experience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC Design Job Summary: We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with...

  • Lead DFT

    3 days ago


    Bangalore, India Angel and Genie Full time

    Role: DFT Lead Experience:10+ years Location: Bangalore Salary: Can be discussed Job Description We are looking for an energetic, passionate and process oriented DFT Leads who has extensive experience in planning, implementation and verification of DFT features for multiple SoC. Direct Responsibilities of the role, but not limited to, working on various...

  • Lead DFT

    4 days ago


    bangalore, India Angel and Genie Full time

    Role: DFT LeadExperience:10+ yearsLocation: BangaloreSalary: Can be discussedJob DescriptionWe are looking for an energetic, passionate and process oriented DFT Leads who has extensive experience in planning, implementation and verification of DFT features for multiple SoC.Direct Responsibilities of the role, but not limited to,working on various aspects of...

  • Senior DFT Engineer

    1 week ago


    bangalore, India L&T Technology Services Full time

    L&T Technology is hiring for Senior DFT Engineers / Lead DFT Engineer with 8-15 Years of experience. Job Location : Bangalore Skills Expertise should be : ATPG, SOC, ASIC DFT.

  • DFT Engineer

    2 weeks ago


    Bangalore, India ACL Digital Full time

    Job Title: DFT Engineer Experience Level: 4+ years Location: Hyderabad/Banglaore Job Description: Key Responsibilities: Develop and implement DFT architecture and methodologies for ASIC/SoC designs. Insert and verify scan chains (scan insertion, ATPG, scan stitching). Implement MBIST/Logic BIST using industry-standard tools and flows. Work on boundary scan...


  • bangalore, India Capgemini Engineering Full time

    Role: DFT Engineer Experience: 4 to 12 Years Location: Bengaluru Job Description: Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes...


  • bangalore, India Capgemini Engineering Full time

    Role: DFT Engineer Experience: 4 to 12 Years Location: Bengaluru Job Description: Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes...