Lead DFT Engineer
11 hours ago
Job Title: Lead DFT EngineerExperience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC DesignJob Summary:We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.Key Responsibilities:Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as:Synopsys: DFT Compiler, TetraMAX, TestMAXSiemens EDA: Tessent ScanPro, MBIST, IJTAGCadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?Lead DFT for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to sharmila.b@acldigital.com
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Lead DFT Engineer
1 day ago
bangalore, India Tech Mahindra Full timeOpen position:- Lead DFT Engineer Experience: - 7+ years Location:- Bangalore NP: - Immediate to 15 days JD: - 1. Experience with DFT tools such as Synopsys DFT Compiler, Test Kompress and Xelium. 2. Minimum 7+ years of experience in DFT engineering, with a focus on Scan Insertion and ATPG, ICL, SSN 3. Strong knowledge of DFT techniques such as Scan Chains,...
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Lead DFT Engineer
1 week ago
bangalore, India ACL Digital Full timeJob Title: Lead DFT Engineer Experience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC Design Job Summary: We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers,...
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Lead Dft Engineer
1 week ago
Bangalore, Karnataka, India Evnek Technologies Full timeJob Title Lead DFT Engineer Location Bengaluru Experience 12 Years Notice Period 30days Role Overview We are seeking an experienced Lead DFT Engineer to drive the integration and optimization of Design-for-Test DFT architecture in our LiDAR SoCs In this role you will own DFT strategy planning implementation and validation across our...
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Dft- sr. lead
4 days ago
Bangalore, India HCLTech Full timeDesign for Testability (DFT) Engineer (Senior Level - 10+ years’ experience) Job Summary: We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and So C projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the...
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DFT- Sr. Lead
1 day ago
bangalore, India HCLTech Full timeDesign for Testability (DFT) Engineer (Senior Level - 10+ years’ experience) Job Summary: We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the...
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DFT- Sr. Lead
4 days ago
bangalore, India HCLTech Full timeDesign for Testability (DFT) Engineer (Senior Level - 10+ years’ experience)Job Summary:We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the...
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DFT Lead
3 days ago
bangalore, India Tech Mahindra Full timeHi Tech Mahindra hiring DFT Engineers for Bangalore location. Exp: 9-14yrs Location: Bangalore NP: 0-45days JD: 1. Experience with DFT tools such as Synopsys DFT Compiler, TestKompress and Xelium 2. 7+ years of experience in DFT engineering, with a focus on Scan Insertion and ATPG, ICL, SSN 3. Strong knowledge of DFT techniques such as Scan Chains, ATPG,...
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Dft lead engineer
2 weeks ago
Bangalore, India 7Rays Semiconductors Full timeJob Description- The candidate is expected to have clear understanding of IJTAG, P1500 protocols and should have hands on experience of at least one of these. The candidate is expected to have clear understanding of BSCAN, MBIST, SCAN, ATPG and Simulation concepts. Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and...
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DFT Lead Engineer
1 day ago
bangalore, India 7Rays Semiconductors Full timeJob Description- The candidate is expected to have clear understanding of IJTAG, P1500 protocols and should have hands on experience of at least one of these. The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts. Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations,...
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DFT Lead Engineer
1 day ago
Bangalore, India ACL Digital Full timeDFT Lead : Work Location - Bangalore Experience - 7+ Years Desired Skills and Experience – · 7+ years of experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. · DFT logic integration and verification. · Experience in debugging low coverage and DRC fixes · Gate Level ATPG simulation with and without timing. · Pattern...
