Digital Full-Chip Test Specialist

Job SummaryWe are seeking an accomplished Digital Full-Chip Test (DFT) Lead Engineer to spearhead our DFT initiatives. This role demands a technical expert with strong leadership skills, excellent communication abilities, and in-depth knowledge of Synopsys/Mentor/Cadence DFT tools.

Job Description:The ideal candidate will be responsible for driving timing closure activities for complex System-on-Chips (SoCs) and providing technical guidance to junior engineers. This involves strong expertise in full-chip timing, constraint management, and cross-functional collaboration.Manage functional and test constraints at block and top...

Timing Closure SpecialistThe ideal candidate will drive timing closure activities for complex SoCs and provide technical guidance to junior engineers.Manage functional and test constraints at block and top levelPerform static timing analysis (STA) for block-level and full-chip sign-offOwn ECO generation at the top level and coordinate with block owners for...

Lead DFT EngineerWe are seeking a highly skilled and experienced lead engineer to spearhead our Digital Fault Tolerance (DFT) initiatives. This is an exceptional opportunity for a talented individual to take ownership of PMBIST planning, insertion, verification, and closure.PMBIST architecture and integrationATPG, fault models, scan insertion, pattern...

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