Principal ASIC Test Architect

6 days ago

bareilly, India beBeeDftLead Full time

Job Title: Lead DFT EngineerWe are seeking an experienced Technical Lead for DFT Architecture and Planning to drive the development of complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.Develop and implement DFT strategies and architectures for multiple ASIC/SoC projects.Design and verify DFT features such as scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan, and IJTAG.Manage the DFT flow from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Generate patterns, simulate faults, and debug test coverage gaps.Ensure DFT signoff, timing closure, and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.The ideal candidate should have 7+ years of experience in DFT for complex ASIC or SoC designs, expertise in scan insertion, compression, ATPG, MBIST, and boundary scan, and hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence.Requirements:B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.

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