Vlsi - physical design lead/staff engineer
4 weeks ago
• Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies.
• Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5 G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies.
• We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows.
• Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity
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Job Title/Role: Physical Design Principal/Staff Engineer
Location : Bangalore/Hyderabad/Ahmedabad
Experience Level : 10+ Years
Industry : Semiconductors
Employment Type : Full-time
Job Functions : Engineering
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Summary
Become a leader on a development team working on an advanced mixed signal chip for a high profile Silicon Valley startup.
This position is for a senior-level Chip Design Lead that will
• Lead the implementation of a complex mixed-signal So C
• Build and guide a team of implementation engineers
• Work with external IP vendors to integrate blocks into the design
• Ensure that each aspect of the design meets the specified requirements
Key Qualifications
Technical
• Experience in all phases of the IC design process from RTL- GDS2
• Analog/Mixed/Custom Signal PNR experience preferred to help drive partitioning for digital and mixed signal So Cs
• Preferably TSMC 7nm PNR sign-off experience using a full COT flow from RTL/gate to GDS
• Experience in developing PNR methodology/flow to and supporting a larger PD team
• Hierarchical Place & Route experience
• Experience in Floorplanning, clock & power network architecture and design
• Experience in UPF/CPF power intent flow – multiple supply domains (bump, deca, power switch placement methods)
• Thorough understanding of digital design, timing analysis, and DFT
• Thorough understanding of LVS/DRC/ERC, EMIR (static & dynamic)
• Knowledge of FCBGA I/O ring layout
• EDA Tools: Cadence (Innovus, Voltus), Mentor (Calibre), Ansys (Redhawk, Totem)
Experience
• BTech/MTech/Ph D with 10-15 years’ experience in chip implementation and 3-5 years as a top-level lead.
• Proven track record with multiple successful final production tape-outs at 16/14nm, 10nm, preferably 7nm
• Knowledge of and experience with embedded processors
• Knowledge of and experience with high-speed interfaces and memory controllers
• Ability to contribute to and guide the development process to meet stringent industry segment requirements.
• Experience with automotive-qualified designs
• Proven ability to deliver results in a very fast-moving startup environment
• Eager to learn & implement ground breaking new hardware technology
• Must be able to solve complex problems and independently drive tasks to completion in a timely manner.
• Be able to work under limited supervision and take complete accountability.
• Excellent written and verbal communication skills
What's in it for you
• Work on leading edge technologies
• An opportunity for career development and growth
• Competitive compensation
• Medical Benefits and more
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