Static timing analysis engineer

1 month ago

Ahmedabad, India Eximietas Design Full time
About Us:
Eximietas Design , a technology driven company headquartered in San Jose, CA with a global footprint that extends to Bangalore, Chennai, Bhubaneswar, Hyderabad and Ahmedabad in India. Eximietas Design is a leading technology firm specializing in ( VLSI / Cloud Computing / Cyber Security / AI / ML ) solutions. With a commitment to innovation and excellence, we empower businesses to thrive in the dynamic digital landscape. Our success is fueled by the expertise of our engineering leadership team, drawn from industry giants such as Google, Cisco, Microsoft, Oracle, Uber, Broadcom, and Sun.
Responsible to be part of STA engineers and close high frequency, lower tech node complex designs.
Full chip timing analysis from early investigation to final implementation and tape out.
Propose or develop timing methodologies to support the timing flow from RTL synthesis to implementation and timing closure.
Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team.
Work with physical design team to improve interface and clock latency.
Work on SDC for block, partition, fullchip such as define constraints, IO budgeting, merging constraints.
Work with third party IP, derive timing signoff requirements.
Requirements:
Bachelor's or Master's degree in Electrical Engineering or Electronics & Communications.
Preferred qualifications:
Min 4 years of experience in STA with ASIC exposure.
Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of Fin FET technology.
Has at least worked on 2+ full chip STA closure of large size silicon.
Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration.
Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power.
Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF.
Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues.

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