Lead Design Verification Engineer
1 day ago
Job Summary:
We are seeking a Lead Design Verification Engineer with expertise in UVM and System Verilog to develop and execute comprehensive verification strategies for complex projects.
Main Responsibilities:
- Lead and manage design verification efforts for complex projects, ensuring successful execution of verification plans.
- Develop test plans and test benches for high-speed peripherals like PCIe, Ethernet, CXL, MIPI, DDR, and HBM.
- Collaborate with cross-functional teams, including architects, designers, and pre/post-silicon verification teams.
- Conduct gate-level simulations and analyze System Verilog assertions and coverage.
- Provide technical guidance to junior verification engineers.
Required Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field.
- Expertise in UVM and System Verilog.
- Prior experience working on IP level and SOC level verification projects.
- Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration.
Estimated Salary: $150,000 per year
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