Memory Compiler Designer

2 months ago


Bengaluru, Karnataka, India ACL Digital Full time
Senior Memory Design Engineer

ACL Digital is seeking a highly skilled Senior Memory Design Engineer to join our team. As a key member of our design team, you will be responsible for developing memory compilers and memory Fast Cache instances for our next-generation Cores, achieving outstanding Power, Performance, and Area (PPA) metrics.

Key Responsibilities:
  • Design and develop memory compilers and memory Fast Cache instances for our next-generation Cores.
  • Collaborate with cross-functional teams to ensure seamless integration of memory designs with other system components.
  • Develop and maintain technical documentation, including design specifications, test plans, and design verification reports.
  • Contribute to the development of design methodologies and tools to improve design productivity and quality.
  • Work closely with the design verification team to ensure that memory designs meet the required specifications and standards.
Requirements:
  • Strong understanding of computer architecture and concepts.
  • Basic understanding of CMOS Transistors and their behaviors.
  • Understanding of high-speed/low-power CMOS circuit design, clocking schemes, static, and complex logic circuits.
  • Understanding of power versus performance versus area trade-offs in typical CMOS design.
  • Excellent interpersonal and communication skills.
  • Minimum 2 years of experience in SRAM/memory design, margin, char, and quality checks.
Nice to Have:
  • Basic scripting languages, e.g., Perl/TCL/Python.
  • Experience with Cadence or Synopsys flows.
  • Experience with circuit simulation and optimization of standard cells.

Interested candidates can apply by sharing their profile at Krishnaprasath.s@acldigital.com



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