Memory Layout Architect

2 days ago


Bengaluru, Karnataka, India UST Full time

At UST, we are seeking a skilled Memory Layout Architect to join our team. The ideal candidate will have hands-on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context.

The selected individual should have expertise in working on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies. They must also have a good handle on IR/EM related issues in memory layouts and be proficient in using Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.

In this role, the successful candidate will work closely with cross-functional teams to deliver high-quality memory compilers. Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines are essential. Experience with memory compilers is highly desirable.

A bachelor's degree in Computer Science, Electrical Engineering, or a related field is required. Additionally, the candidate should possess excellent communication skills and be able to effectively collaborate with external customers and internal stakeholders.

We offer a competitive salary package, including a base salary of $120,000 - $150,000 per annum, depending on experience, plus additional benefits such as health insurance, retirement savings plan, and paid time off.



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