Senior Design for Test

1 day ago

Rajahmundry, Andhra Pradesh, India beBeeArchitect Full time ₹ 15,00,000 - ₹ 21,37,000
Job Title: Senior Design for Test (DFT) Architect

We are seeking a highly skilled Senior DFT Architect to drive the architecture, planning, and implementation of complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.

Key Responsibilities:
  1. DFT Strategy and Architecture: Define and drive DFT strategy and architecture for multiple ASIC/SoC projects, ensuring seamless integration with RTL, STA, PD, and test engineering teams.
  2. DFT Features Implementation: Lead the implementation and verification of DFT features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).
  3. DFT Flow Management: Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up, maintaining high-quality standards throughout.
  4. Collaboration and Leadership: Collaborate with cross-functional teams to drive design excellence, mentor junior DFT engineers, conduct design reviews and training sessions, and foster a culture of innovation.
  5. Automation and Tools: Develop and maintain DFT automation scripts and infrastructure, enhancing productivity and efficiency across the organization.
Required Skills and Experience:
  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs, with expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.
  • Strong knowledge of RTL design, STA, and synthesis flows, with proficiency in scripting languages (Python, Perl, Tcl) for flow automation.
Preferred Qualifications:
  • Experience with hierarchical DFT and low-power DFT methodologies (UPF), ensuring power-efficient designs.
  • Exposure to post-silicon validation and failure analysis, driving root cause identification and corrective action.
  • Familiarity with safety-critical designs (ISO 26262) and functional safety, ensuring compliance and reliability.

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