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Distinguished Digital Fault Tolerance Expert

2 weeks ago

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Job Overview

Lead a Team in Digital Fault Tolerance

We seek an accomplished professional to assume the role of DFT Lead. This leadership position requires an individual with exceptional expertise in digital fault tolerance concepts.

The successful candidate will possess extensive knowledge in scan insertion, ATPG (Automatic Test Pattern Generation), coverage analysis, transition delay test coverage analysis, MBIST (Memory Built-In Self-Test) insertion, and memory test validation.

They should also be proficient in test mode timing constraints definition, scripting languages such as Perl and shell, RTL (Register-Transfer Level) and gate-level simulations of scan and MBIST test vectors, equivalence check, DFT DRC (Design Rule Check) rules, and experience working with Synopsis TetraMax/DFTMax and Cadence Encounter Test.

This leader will facilitate teamwork, adaptability to new tools and methodologies, multitasking, and collaboration on high-priority designs in parallel. Excellent problem-solving skills, effective communication, and teamwork are essential for success.

Strong English language proficiency is required for this position.