Senior Digital Fault Tolerance Engineer

1 day ago

Belgaum, Karnataka, India beBeeDft Full time ₹ 25,00,000 - ₹ 31,00,000
Job Title

About the Role

  • Drive DFT architecture definition and implementation for complex SoCs.
  • Plan, execute, and deliver scan, ATPG, MBIST, and boundary scan insertion and validation.
  • Work with EDA vendors to evaluate, deploy, and optimize DFT tool flows.
  • Automate repetitive tasks using scripting to improve efficiency and reduce errors.
  • Support test vector generation and validation for ATE.
  • Provide technical guidance and mentorship to junior engineers in the DFT team.

Requirements

  • 3+ years of experience in DFT architectures and methodologies.
  • Strong expertise in Scan Insertion & Verification, ATPG, MBIST, JTAG / Boundary Scan.
  • Hands-on experience with industry-standard DFT tools and methodologies from Cadence, Synopsys, and Mentor Graphics (Siemens EDA).
  • Proven ability to develop and debug scripting solutions using Python, Perl, and TCL for automation of DFT flows.
  • Solid understanding of SoC design cycle, RTL to GDSII flow, and test requirements.
  • Experience collaborating with RTL designers, verification engineers, and physical design teams to ensure seamless DFT integration.
  • Strong problem-solving skills, ability to debug complex test issues, and deliver high-quality DFT solutions within tight schedules.

Preferred Skills

  • Knowledge of low-power DFT techniques (power-aware ATPG, retention flops, etc.).
  • Experience with post-silicon bring-up and ATE patterns.
  • Familiarity with safety-critical standards (ISO 26262, DO-254, etc.).
  • Exposure to High-Speed IO testing (SERDES, DDR, etc.).

About Our Team

We are a team of experts in DFT looking for talented individuals to join us. If you have experience in designing and implementing DFT architectures, we want to hear from you.

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