Senior Digital Fault Tolerance Engineer

5 days ago

Alleppey, Kerala, India beBeeDigitalFaultTolerance Full time ₹ 18,00,000 - ₹ 30,00,000

Job Title:

We are seeking an experienced DFT Lead to join our team at a prominent semiconductor company. The successful candidate will have a strong background in digital fault tolerance and be able to provide expert guidance on test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.

About the Role:

  • In-depth knowledge of DFT concepts, including scan insertion, ATPG, coverage analysis, transition delay test coverage analysis, MBIST insertion, and memory test validation.
  • Expertise in scripting languages such as Perl, shell, etc.
  • Experience in RTL and gate-level simulations of scan and MBIST test vectors.
  • Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like Spyglass) and ATPG tool like (TetraMax).
  • Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus.
  • Ability to work in an international team, dynamic environment.
  • Ability to learn and adapt to new tools and methodologies.
  • Excellent problem-solving skills.
  • Excellent communication and teamwork skills, with good English proficiency required.

Key Responsibilities:

  • Lead the development of DFT strategies and implementation plans
  • Collaborate with cross-functional teams to ensure seamless integration of DFT solutions
  • Develop and maintain complex test plans and scripts
  • Analyze and troubleshoot test results
  • Provide training and support to junior engineers

Requirements:

  • 7-15 years of experience in DFT engineering
  • Strong understanding of digital circuit design principles
  • Hands-on experience with various DFT tools and technologies
  • Ability to multitask and work on multiple high-priority designs in parallel

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