Lead Timing Closure Specialist

5 days ago

Kannur, Kerala, India beBeeTiming Full time ₹ 25,00,000 - ₹ 30,00,000

Job Title: Lead Timing Closure Specialist

 

Job Description:

As a seasoned engineer, you will lead the Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your focus will be on achieving robust timing closure and physical implementation with an emphasis on power, performance, and area optimization.

 

Main Responsibilities:

  • Develop and refine methodologies tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems
  • Drive automation and validation of timing and physical design data across subsystem boundaries
  • Mentor junior engineers, fostering technical growth and knowledge sharing within subsystem teams
  • Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration

 

Qualifications and Skills:

We are looking for someone with 10+ years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).

The ideal candidate should have demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.

They should also have a proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.

A proficient scripting language skillset (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks is essential.

A deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems, is also required.

Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level is preferred.

Background in high-speed interfaces or mixed-signal SoC subsystems is beneficial.

 

Bonus Points:

  • Advanced knowledge of low-power design techniques
  • Expertise in formal verification tools (e.g., SymbiYosys)
  • Familiarity with cloud-based design platforms

 

About This Opportunity:

This role offers a challenging and dynamic work environment where you will be part of a talented team of engineers working together to deliver cutting-edge solutions.

You will have opportunities to grow professionally and develop your skills through training and mentorship programs.

We value innovation, teamwork, and continuous improvement, and we are committed to providing a positive and inclusive work environment.

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