Lead Static Timing Analyst

5 days ago

Kannur, Kerala, India beBeeTiming Full time ₹ 45,00,000 - ₹ 55,00,000
Senior Timing Engineer Opportunity

We are seeking a skilled Senior Timing Engineer to join our team. In this role, you will be responsible for leading the development of prime time constraints and implementing clean-up measures at the full chip level.

Key Responsibilities:

  • Perform netlist and constraint sign in checks and validation.
  • Develop prime time constraints at full chip level and implement clean-up measures.
  • Apply multimode multi-corner timing knowledge for sub HM/block/top level timing closure.
  • Closely collaborate with cross-functional teams to ensure top-level timing closure, incorporating Xtalk and OCV considerations.
  • Develop ECO implementation strategies for netlist, RTL, and timing level changes using scripting languages like Perl/TCL.
  • Demonstrate exceptional debugging skills to resolve implementation issues and devise creative solutions.
  • Stay up-to-date with the latest technologies from 28nm and below.
  • Possess a minimum of 8+ years of experience in STA and synthesis, with expertise in timing constraints.
  • Familiarity with tools like Primetime or Tempus is essential.

Requirements:

  • Strong understanding of digital design principles and methodologies.
  • Expertise in static timing analysis (STA) and synthesis.
  • Experience working with timing constraints and netlists.
  • Excellent problem-solving skills and attention to detail.
  • Ability to work collaboratively in a team environment.

What We Offer:

  • A dynamic and supportive work environment.

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