
Circuit Architect
15 hours ago
As a Senior Memory Design Engineer, you will play a key role in developing memory compilers and memory Fast Cache instances for our next-generation Cores, achieving outstanding PPA.
- We are looking for an engineer with strong understanding of computer architecture and concepts.
- Candidate should have basic knowledge of CMOS Transistors and their behaviors.
- Experience in high-speed/low-power CMOS circuit design, clocking scheme, Static and complex logic circuits is required.
- Understanding of Power versus Performance versus Area trade-offs in typical CMOS design is essential.
- Candidate must have engineering demeanor and passion for Circuit design.
- Good interpersonal skills are necessary.
Responsibilities:
Developing memory compilers and memory Fast Cache instances for our next-generation Cores
Implementing high-speed/low-power CMOS circuit design
Designing clocking schemes for static and complex logic circuits
Optimizing performance, power consumption, and area trade-offs in typical CMOS design
Requirements:
- Minimum 2 years of experience in SRAM/memory design margin, char, and its related quality checks
- Basic understanding of scripting languages (e.g., Perl/TCL/Python)
- Experience working on Cadence or Synopsys flows
- Knowledge of circuit simulation and optimization of standard cells
Nice To Have Skills:
- Knowledge of basic scripting languages (e.g., Perl/TCL/Python)
- Experience working on Cadence or Synopsys flows
- Knowledge of circuit simulation and optimization of standard cells
Interested candidates can apply/share/refer profile at Krishnaprasath.s@acldigital.com.
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