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5 days ago
As a Senior DFT Lead Architect, you will be responsible for leading the development and implementation of comprehensive Design for Test (DFT) strategies.
This includes collaborating with ASIC design teams to ensure that DFT design rules and coverages are met, generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models through the use of on-chip test compression techniques, and conducting MBIST verification (including repair), test pattern generation through Mentor tool.
You will also be responsible for working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE and supporting post-silicon debug efforts, including issue resolution.
Furthermore, you will develop, enhance, and maintain scripts as necessary.
Required Skills and Qualifications
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field.
- Minimum of 4 to 12 years' experience in ASIC/DFT - simulation and Silicon validation.
- Detailed knowledge on DFT concepts, pattern simulation, Silicon debug, and yield enhancement.
- In-depth knowledge and hands-on experience in ATPG - coverage analysis.
- Experience with any of these tools is required: TestKompress, ETVerify, VCS (preferred), ModelSim.
- Expertise in scripting languages such as Perl, shell, etc. is an added advantage.
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