Senior Chip Designer

5 days ago


Nellore, Andhra Pradesh, India beBeePhysical Full time ₹ 1,44,00,000 - ₹ 2,16,00,000

Job Summary

We are seeking a skilled Physical Design Engineer to undertake all aspects of Physical Design for Fullchip/Blocks, including Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.

The ideal candidate will have sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.

The successful candidate will possess excellent communication and presentation skills, as well as good interpersonal skills and problem-solving ability.

Key Responsibilities

  • Undertake all aspects of Physical Design for Fullchip/Blocks
  • Have sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.
  • Possess excellent communication and presentation skills, as well as good interpersonal skills and problem-solving ability.

Requirements

  • 4+ years experience in ASIC physical design
  • Experience with block implementation, extraction, timing and or full-chip designs
  • Strong communication skills
  • Strong hands-on TCL/Perl development skills

Preferred Qualifications

  • Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project
  • Track record of taping out complex chips on advanced process nodes


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