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Advanced Mixed-Signal Chip Timing Expert
3 weeks ago
Synthesis and Static Timing Analysis Staff Design Engineer/Design Manager
Company Overview:
Eteros Technologies is a Semiconductor Engineering services startup with worldwide customers among the top semiconductor companies.
Our engineers work on cutting-edge technology nodes in AI/ML Datacenter Automotive and 5G domains showcasing their skills globally while learning from respected companies.
We are not a traditional design services company offering staff augmentation; our engineers are integral to customer teams responsible for turnkey ownership and delivery across implementation verification DFT and analog design.
Eteros invests in our engineers providing continuous learning opportunities and career growth support.
- Key Responsibilities:
- Lead synthesis static timing and DFT efforts for an advanced mixed signal chip.
- Interface with all disciplines for critical impact in getting functional products to customers quickly.
- Develop and maintain methodology and flows related to timing verification and closure.
- Analyze timing reports and utilize scripting techniques to drive rapid timing closure.
Requirements:
- Bachelor's Master's or Doctoral degree in relevant field with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure.
- Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV noise and crosstalk effects on timing.
- Familiarity with all aspects of timing closure of high-performance mixed-signal SoCs in advanced finFET technology nodes preferably 7nm.
- Knowledge of timing corners/modes and process variations.
- Knowledge of low-power techniques including clock gating power gating and millivoltage designs.
- Proficient in scripting languages (Tcl and Perl).
