Timing Closure Expert

1 week ago

Nellore, Andhra Pradesh, India beBeeDesign Full time ₹ 15,00,000 - ₹ 25,00,000
Job Description

We are seeking an experienced Design Engineer/Design Manager to lead our Synthesis and Static Timing efforts for a cutting-edge mixed-signal chip. As a key member of our team, you will be responsible for developing and maintaining methodologies and flows related to timing verification and closure.

Key responsibilities include:

  • Ownership of full-chip and block-level timing closure throughout the project cycle.
  • Generation of block and full-chip timing constraints.
  • Analysis of timing reports and development of insights through scripting techniques.
Required Skills and Qualifications

To succeed in this role, you should have:

  • A BTech/MTech/PhD degree with at least 6+ years of hands-on experience in ASIC timing constraints generation and timing closure.
  • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise, and crosstalk effects on timing.
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes.
  • Knowledge of timing corners/modes and process variations.
  • Proficiency in scripting languages (Tcl and Perl).
Benefits

This is a unique opportunity to work on leading-edge technologies and contribute to the development of advanced mixed-signal chips. As a Staff Design Engineer/Design Manager, you will be part of a highly talented team and have critical impact in getting functional products to customers quickly.

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