Senior Technical Development Manager

7 days ago

Jamnagar, Gujarat, India beBeeInnovative Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
Job Description:

Silicon Labs is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. The company merges cutting-edge technology into the world's most highly integrated SoCs, providing device makers with the solutions, support, and ecosystems needed to create advanced edge connectivity applications.

Responsibilities:
  • Lead the development and execution of Wireless SoC's from definition, through execution, and into production
  • Coordinate with product marketing teams to develop SoC requirements
  • Develop and maintain SoC architecture or technical specification to meet product requirements
  • Develop design schedule, including milestones and resource requirements
  • Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross-functional teams
  • Actively support validation and product test teams during silicon bringup, validation, characterization, and qualification

The chosen candidate would need to contribute to, and manage a team for, the development of architecture, microarchitecture, and design of SoCs which include RISC-V, ARM or proprietary processor designs, along with the integration of wireless systems, power management, and mixed-signal IP.

Requirements:
  • Capable of leading complex IP, SOC development projects' execution
  • Top-down planning and execution of SOC projects
  • Experience in full-chip development cycle
  • Able to build strong technical team
  • Hands-on experience in architecture, micro-architecture, digital design processes
  • Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
  • Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc.
  • Knowledge of processors like RISC-V and ARM processors
  • Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
  • Knowledge of DFT including Scan, ATPG, MBIST
  • Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
  • Knowledge of hardware accelerators
  • Knowledge of Verilog and System Verilog
  • Knowledge of scripting languages like Perl, Python, Tcl, shell
Benefits and Perks:
  • Equity Rewards (RSUs)
  • Employee Stock Purchase Plan (ESPP)
  • Insurance plans with Outpatient cover
  • National Pension Scheme (NPS)
  • Flexible work policy
  • Childcare support

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