Design Verification Engineer

4 weeks ago


Pune, Maharashtra, India Cadence Design Systems, Inc. Full time

Cadence Design Systems, Inc. is seeking a talented Design Verification Engineer to join our team.

Job Summary:

  • Develop complex test benches in System Verilog using OVM/UVM methodology.
  • Coding functional coverage and system verilog assertions.
  • Validation of protocols such as AXI4, AHB, functionality like DMA (Direct Memory Access Controllers), Arbiters.
  • Knowledge of computer architecture, AI accelerators is a big plus.
  • Well versed with System Verilog and popular EDA (Cadence Xcelium preferred) simulation, System Verilog assertions and testbench methodologies.
  • Exposure to scripting languages like Perl, Unix shell or similar languages.
  • Excellent written and oral communication skills necessary.

Responsibilities:

  • Part of design verification team supporting the DNA (Deep Neural Accelerator) product line.
  • Work closely with designers/micro-architect to understand the design.
  • Work on complete or part of the verification plan, review the same with others in the team.
  • Develop the verification infrastructure and carryout validation.
  • Log/Track and validate defects.

Requirements:

  • B.E/B.Tech 2+ years of experience in Design Verification or M.E/M.Tech (full time).

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