Verification Engineer

1 month ago


Pune, Maharashtra, India Lattice Semiconductor Full time
Overview

Lattice Semiconductor is a leading provider of programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Responsibilities & Skills

Responsibilities:

We are seeking a highly skilled Verification Engineer to join our Silicon Engineering team. As a key member of our team, you will have the opportunity to contribute to verifying complex FPGAs and integrate multiple sophisticated IP level Design and Verification (DV) environments. You will craft highly reusable best-in-class UVM test benches, implement effective coverage driven and directed test cases, and deploy new tools and methodologies to improve quality of tape-out readiness.

Required Skills:

  • BS/MS Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree.
  • At least 8+ years DV experience out of which 3+ years as leading a complex IP verification.
  • Proven track record of working full ASIC verification from concept to tape-out.
  • Advanced knowledge of System Verilog and UVM methodology.
  • Experience in using programming languages such as C/C++, Perl/Python/Tcl for automatic the DV tasks.
  • Hands-on verification experience in verifying IPs using AMBA bus architecture in UVM environment.
  • Hands-on verification experience in verifying the firmware used for SOC functions.
  • In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.
  • Ability to create IP level module and sub-system verification plans, TBs, portable test benches, sequences, verification infrastructure.
  • Develop UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and verification suites at SOC level, and achieve targeted coverage.
  • Work with design, architecture, SW, FW, and IP delivery teams to efficiently integrate and verify overall FPGA design.
  • Should be a great team leader with excellent communication and problem-solving skills and the desire to seek diverse challenges.


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