Highly Skilled Principal Design Engineer Wanted
2 weeks ago
Job Description:
As a Senior Principal Design Engineer at Cadence Design Systems, Inc., you will be responsible for leading the design of complex IP's and SoC's at 16/10/7 nm. Our ideal candidate has a strong background in physical design, timing closure, and physical verification, with hands-on experience in Cadence implementation tools such as Genus, Innovus, Quantus, Tempus, PVS, and Voltus.
Requirements:
- B.Tech/BE/ME/Mtech with expertise in physical design, timing closure, and physical verification.
- Exp. with ASIC design flow, hierarchical physical design strategies, methodologies, and deep sub-micron technology issues.
- Solid knowledge on physical design flow, timing closure, and physical verification. Knowledge of formal verification, EM-IR.
- Good track record of working on complex IP's and SoC's at 16/10/7 nm.
- Power user of Cadence implementation tools.
- Automation and programming-minded, with coding experience in Makefile/Tcl/Tk/Perl.
- Self-motivated, able to work independently or as a team player, with excellent verbal and written communication skills.
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